Actuation and Limits of Self-Aligned Electromechanical Switches

We demonstrate a large aspect ratio self-aligned silicon nanopillar electromechanical switch achieved with a single lithography step. This compact vertical device can be aggressively scaled by virtue of self-limiting oxidation. We describe a scaling relation that outlines the design space for this class of low voltage nanorelays. Summary of Research: We summarize: (a) the implications of electrostatic and electromechanical coupling connected through pullin; (b) the implications of geometry on capacitance, electrostatics and electrostatic forces; (c) the implication of impact forces in operation, and (d) the limits of characteristics that are likely to be achievable in a silicon-based electromechanical switch. In experimental self-aligned structures fabricated with gaps on the order of 200 nm, operating voltages below 15 V are achieved; scalable to lower voltages, but making structures that are not limited to single-program operation due to momentum-induced fusing will be a challenge. Our device, a nanorelay, uses the mechanical actuation of a channel to bridge the gap between source (S) and drain (D) electrodes (Figure 1). A pillar (gate G) is attached to a floating conductor (channel C) by way of a thin insulating spacer. The capacitances CCS and CGC form a voltage divider which determines the potential of C, and the electrostatic force on the channel is proportional to VCS 2. Two modes of operation are exhibited depending on the ratio CCS/CGC. For CCS < 2CGC, as the voltage is increased quasi-statically, the pillar reaches an unstable equilibrium at a certain distance, following which it rapidly pulls-in to make contact, whereas for CCS ≥ 2CGC, the pillar remains in stable equilibrium throughout and makes contact smoothly. A device configuration with a side gate (G′) was also considered, which potentially allows for additional control, but the electrostatic force on the channel due to G′ decreases the net force in the direction of the S/D, thus increasing the voltage of initial actuation. We explore the vast parameter space of these devices, with the actuation voltage as the primary figure of merit, which we estimate analytically based on the capacitive divider model neglecting fringe fields. In Figures 2 and 3, we show the relative variation of the actuation voltage with each of the device parameters defined in Figure 1, while the others are held constant. The base point is for a typical experimental geometry close to the critical pull-in criterion. The simplest possibility is constant field (l) scaling which reduces the voltage Figure 1: Device schematic and dimensionless scaling parameters. Side gate G′ is not present on some devices.